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author | 2024-04-08 08:34:02 +0200 | |
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committer | 2024-04-08 08:34:02 +0200 | |
commit | 95d054edad1b81d99c364740837f7e06c94047f6 (patch) | |
tree | 0ffcb5bde18f0c95424f2f11a0a69b66b0d8c858 | |
parent | Add some more riscv links (diff) | |
download | www-95d054edad1b81d99c364740837f7e06c94047f6.tar.gz www-95d054edad1b81d99c364740837f7e06c94047f6.tar.bz2 www-95d054edad1b81d99c364740837f7e06c94047f6.zip |
Minor text improvements
Signed-off-by: Andreas K. Hüttel <dilfridge@gentoo.org>
-rw-r--r-- | _includes/downloads/riscv.html | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/_includes/downloads/riscv.html b/_includes/downloads/riscv.html index b7ea81b..06e38b9 100644 --- a/_includes/downloads/riscv.html +++ b/_includes/downloads/riscv.html @@ -5,6 +5,10 @@ <p> The <em>lp64d</em> stages can be used on all 64-bit RISC-V processors supporting the <strong>double-precision floating point</strong> instruction set. The <em>lp64</em> stages can be used on all 64-bit RISC-V processors; they require no hardware support for floating point arithmetics. + Multilib stages include toolchain support for all 64-bit and 32-bit ABI and are based on lp64d. They are mostly useful for development and testing purposes. + <br> + The <em>ilp32d</em> stages can be used on all 32-bit RISC-V processors supporting the <strong>double-precision floating point</strong> instruction set. + The <em>ilp32</em> stages can be used on all 32-bit RISC-V processors; they require no hardware support for floating point arithmetics. </p> </div> @@ -17,7 +21,9 @@ {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_multilib-openrc" title="Stage 3" tag="rv64gc | multilib | openrc" %} {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_multilib-systemd" title="Stage 3" tag="rv64gc | multilib | systemd" %} </div> +</div> +<div class="col-xs-12 col-md-6"> <h4>Stage archives (RV32)</h4> <div class="list-group"> {% include partials/download-link.html type="stage3" arch="riscv" id="rv32_ilp32d-openrc" title="Stage 3" tag="rv32gc | ilp32d | openrc" %} @@ -25,9 +31,7 @@ {% include partials/download-link.html type="stage3" arch="riscv" id="rv32_ilp32-openrc" title="Stage 3" tag="rv32gc | ilp32 | openrc" %} {% include partials/download-link.html type="stage3" arch="riscv" id="rv32_ilp32-systemd" title="Stage 3" tag="rv32gc | ilp32 | systemd" %} </div> -</div> -<div class="col-xs-12 col-md-6"> <h4>Musl stage archives</h4> <div class="list-group"> {% include partials/download-link.html type="stage3" arch="riscv" id="rv64_lp64d_musl" title="Stage 3" tag="rv64gc | lp64d | musl | openrc" %} |