blob: 3729264a1e15a4c4994ac23871ef5656b0b8780b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
|
BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4
DEFINED_PHASES=install prepare
DEPEND=dev-util/gperf sys-devel/bison sys-devel/flex sys-libs/readline:0 sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
EAPI=7
HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
IUSE=examples
KEYWORDS=~alpha amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ppc ~ppc64 ~riscv ~s390 sparc x86
LICENSE=LGPL-2.1
RDEPEND=sys-libs/readline:0 sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz -> iverilog-10.3.tar.gz
_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 libtool f143db5a74ccd9ca28c1234deffede96 multilib 98584e405e2b0264d37e8f728327fed1 toolchain-funcs 605c126bed8d87e4378d5ff1645330cb
_md5_=e0d0d3128769a8fc437c0841081f815c
|
GitWeb
