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authorRepository QA checks <repo-qa-checks@gentoo.org>2017-08-27 20:30:34 +0000
committerRepository QA checks <repo-qa-checks@gentoo.org>2017-08-27 20:30:34 +0000
commit867ad2d68a6e56390e95172894bb580a45f95f65 (patch)
treef7fc098bfe8d820960f868b6f4eaabcc86156399 /metadata/md5-cache/sci-electronics/iverilog-0.9.6
parentMerge updates from master (diff)
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2017-08-27 20:30:32 UTC
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-0.9.6')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-0.9.614
1 files changed, 0 insertions, 14 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-0.9.6 b/metadata/md5-cache/sci-electronics/iverilog-0.9.6
deleted file mode 100644
index 49378886ce90..000000000000
--- a/metadata/md5-cache/sci-electronics/iverilog-0.9.6
+++ /dev/null
@@ -1,14 +0,0 @@
-DEFINED_PHASES=install prepare
-DEPEND=app-arch/bzip2 sys-libs/readline sys-libs/zlib
-DESCRIPTION=A Verilog simulation and synthesis tool
-EAPI=4
-HOMEPAGE=http://iverilog.icarus.com/
-IUSE=examples
-KEYWORDS=amd64 ppc sparc x86
-LICENSE=GPL-2
-RDEPEND=app-arch/bzip2 sys-libs/readline sys-libs/zlib
-SLOT=0
-SRC_URI=ftp://icarus.com/pub/eda/verilog/v0.9/verilog-0.9.6.tar.gz
-_eclass_exported_funcs=src_prepare:- src_install:-
-_eclasses_=epatch 8233751dc5105a6ae8fcd86ce2bb0247 estack 43ddf5aaffa7a8d0482df54d25a66a1f eutils 9c113d6a64826c40154cad7be15d95ea ltprune 2770eed66a9b8ef944714cd0e968182e multilib 97f470f374f2e94ccab04a2fb21d811e toolchain-funcs 185a06792159ca143528e7010368e8af
-_md5_=6c390db9e7a005dbbc244949cbec6e42