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From c1d0aadc4440c07d2e940c83c1b6e5d9d694a3a5 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Wed, 29 Mar 2017 15:17:03 +0800
Subject: [PATCH 08/11] fix: pci: aardvark: disable LOS state by default
Some PCIe devices do not support LOS, there will be time out issue
if the RC forces the LOS state.
This patch disables the LOS state by default.
Change-Id: I88a6a5cf58ea5f2df234c99050ce041987cdabc6
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38119
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 37d0bcd31f8a..072bc70e900c 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -365,8 +365,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_pcie_wait_for_link(pcie);
- reg = PCIE_CORE_LINK_L0S_ENTRY |
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
--
2.13.3
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