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Diffstat (limited to 'sys-kernel/armv8multi-sources/files/4.13/0002-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch')
-rw-r--r--sys-kernel/armv8multi-sources/files/4.13/0002-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch35
1 files changed, 35 insertions, 0 deletions
diff --git a/sys-kernel/armv8multi-sources/files/4.13/0002-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch b/sys-kernel/armv8multi-sources/files/4.13/0002-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch
new file mode 100644
index 0000000..c1e62b9
--- /dev/null
+++ b/sys-kernel/armv8multi-sources/files/4.13/0002-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch
@@ -0,0 +1,35 @@
+From 2dc4d4cdd65e437140c1e0816933b3a85244269e Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <Marc.Zyngier@arm.com>
+Date: Sat, 1 Jul 2017 15:16:36 +0100
+Subject: [PATCH 02/14] ARM64: dts: marvell: armada37xx: Wire PMUv3
+
+The Cortex-A53s that power the Armada-37xx SoCs are equipped with
+a PMUv3, just like most ARMv8 cores.
+
+Advertise the PMUv3 presence in the device tree, and wire its
+interrupt. This allows the perf subsystem to work correctly.
+
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+---
+ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+index b6f1e7a5e5ec..35307cd93db5 100644
+--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+@@ -81,6 +81,11 @@
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ pmu {
++ compatible = "arm,armv8-pmuv3";
++ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+--
+2.15.0
+