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author | 2006-06-09 04:22:10 +0000 | |
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committer | 2006-06-09 04:22:10 +0000 | |
commit | c3293ee6f85d0a754173937fdc2d151fc67a8c5b (patch) | |
tree | d01c2b85df5ee18a42823f7a7403e62224687aae /4.1.1 | |
parent | Deal with REG passed to sweep_string_variable - bug #74457 (diff) | |
download | gcc-patches-c3293ee6f85d0a754173937fdc2d151fc67a8c5b.tar.gz gcc-patches-c3293ee6f85d0a754173937fdc2d151fc67a8c5b.tar.bz2 gcc-patches-c3293ee6f85d0a754173937fdc2d151fc67a8c5b.zip |
Update to fix a build error on mips due to the way gcc-4 handles prototypes
Diffstat (limited to '4.1.1')
-rw-r--r-- | 4.1.1/gentoo/91_all_mips-ip28_cache_barriers-v4.patch | 54 |
1 files changed, 40 insertions, 14 deletions
diff --git a/4.1.1/gentoo/91_all_mips-ip28_cache_barriers-v4.patch b/4.1.1/gentoo/91_all_mips-ip28_cache_barriers-v4.patch index 5336f39..95b13e4 100644 --- a/4.1.1/gentoo/91_all_mips-ip28_cache_barriers-v4.patch +++ b/4.1.1/gentoo/91_all_mips-ip28_cache_barriers-v4.patch @@ -1,28 +1,44 @@ diff -Naurp gcc-4.1.1.orig/gcc/config/mips/mips.c gcc-4.1.1/gcc/config/mips/mips.c ---- gcc-4.1.1.orig/gcc/config/mips/mips.c 2006-05-04 16:14:58.000000000 -0400 -+++ gcc-4.1.1/gcc/config/mips/mips.c 2006-05-27 14:20:54.000000000 -0400 -@@ -8919,6 +8919,11 @@ mips_reorg (void) +--- gcc-4.1.1.orig/gcc/config/mips/mips.c 2006-06-07 22:35:02.000000000 -0400 ++++ gcc-4.1.1/gcc/config/mips/mips.c 2006-06-07 22:50:37.000000000 -0400 +@@ -56,6 +56,7 @@ Boston, MA 02110-1301, USA. */ + #include "cfglayout.h" + #include "sched-int.h" + #include "tree-gimple.h" ++#include "r10k-cacheb.c" + + /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */ + #define UNSPEC_ADDRESS_P(X) \ +@@ -408,6 +409,7 @@ static rtx mips_expand_builtin_compare ( + static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx); + static void mips_encode_section_info (tree, rtx, int); + ++ + /* Structure to be filled in by compute_frame_size with register + save masks, and offsets for the current function. */ + +@@ -8959,7 +8961,6 @@ mips_avoid_hazards (void) + } + } + +- + /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ + + static void +@@ -8975,6 +8976,10 @@ mips_reorg (void) if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN) vr4130_align_insns (); } + if (TARGET_R10K_SPECEX) + { -+ static int r10k_insert_cache_barriers (void); + r10k_insert_cache_barriers (); + } } /* This function does three things: -@@ -10764,5 +10769,6 @@ mips_encode_section_info (tree decl, rtx - SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; - } - } -+#include "r10k-cacheb.c" - - #include "gt-mips.h" diff -Naurp gcc-4.1.1.orig/gcc/config/mips/mips.opt gcc-4.1.1/gcc/config/mips/mips.opt --- gcc-4.1.1.orig/gcc/config/mips/mips.opt 2005-07-23 04:36:54.000000000 -0400 -+++ gcc-4.1.1/gcc/config/mips/mips.opt 2006-05-27 14:20:28.000000000 -0400 ++++ gcc-4.1.1/gcc/config/mips/mips.opt 2006-06-07 22:49:22.000000000 -0400 @@ -216,3 +216,13 @@ Perform VR4130-specific alignment optimi mxgot Target Report Var(TARGET_XGOT) @@ -39,8 +55,8 @@ diff -Naurp gcc-4.1.1.orig/gcc/config/mips/mips.opt gcc-4.1.1/gcc/config/mips/mi +Target Undocumented Var(TARGET_R10K_SPECEX) VarExists diff -Naurp gcc-4.1.1.orig/gcc/config/mips/r10k-cacheb.c gcc-4.1.1/gcc/config/mips/r10k-cacheb.c --- gcc-4.1.1.orig/gcc/config/mips/r10k-cacheb.c 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-4.1.1/gcc/config/mips/r10k-cacheb.c 2006-05-27 14:20:28.000000000 -0400 -@@ -0,0 +1,288 @@ ++++ gcc-4.1.1/gcc/config/mips/r10k-cacheb.c 2006-06-07 22:49:54.000000000 -0400 +@@ -0,0 +1,298 @@ +/* Subroutines used for MIPS code generation: generate cache-barriers + for SiliconGraphics IP28 and IP32/R10000 kernel-code. + Copyright (C) 2005,2006 peter fuerst, pf@net.alphadv.de. @@ -65,6 +81,16 @@ diff -Naurp gcc-4.1.1.orig/gcc/config/mips/r10k-cacheb.c gcc-4.1.1/gcc/config/mi + +#define ASM_R10K_CACHE_BARRIER "cache 0x14,0($sp)" + ++static int is_stack_pointer (rtx *x, void *data); ++static int check_p_mem_expr (rtx *memx, void *data); ++static int check_p_pattern_for_store (rtx *body, void *data); ++static int strmatch (const char *txt, const char *match); ++static int check_insn_for_store (int state, rtx insn); ++static int bb_insert_store_cache_barrier (rtx head, rtx nxtb); ++static int scan_1_bb_for_store (rtx head, rtx end); ++static int r10k_insert_cache_barriers (void); ++ ++ +/* Check, whether an instruction is a possibly harmful store instruction, + i.e. a store which might cause damage, if speculatively executed. */ + |