diff options
Diffstat (limited to 'opcodes/i386-reg.tbl')
| -rw-r--r-- | opcodes/i386-reg.tbl | 166 |
1 files changed, 83 insertions, 83 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 61e9fe07c20..8e6a2df2ee5 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -19,82 +19,82 @@ // 02110-1301, USA. // Make %st first as we test for it. -st, Reg|Acc|Tbyte, 0, 0, 11, 33 +st, Class=Reg|Acc|Tbyte, 0, 0, 11, 33 // 8 bit regs -al, Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval -cl, Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval -dl, Reg|Byte, 0, 2, Dw2Inval, Dw2Inval -bl, Reg|Byte, 0, 3, Dw2Inval, Dw2Inval -ah, Reg|Byte, 0, 4, Dw2Inval, Dw2Inval -ch, Reg|Byte, 0, 5, Dw2Inval, Dw2Inval -dh, Reg|Byte, 0, 6, Dw2Inval, Dw2Inval -bh, Reg|Byte, 0, 7, Dw2Inval, Dw2Inval -axl, Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval -cxl, Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval -dxl, Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval -bxl, Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval -spl, Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval -bpl, Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval -sil, Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval -dil, Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval -r8b, Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval -r9b, Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval -r10b, Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval -r11b, Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval -r12b, Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval -r13b, Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval -r14b, Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval -r15b, Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval +al, Class=Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval +cl, Class=Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval +dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval +bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval +ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval +ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval +dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval +bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval +axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval +cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval +dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval +bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval +spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval +bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval +sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval +dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval +r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval +r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval +r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval +r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval +r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval +r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval +r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval +r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval // 16 bit regs -ax, Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval -cx, Reg|Word, 0, 1, Dw2Inval, Dw2Inval -dx, Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval -bx, Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval -sp, Reg|Word, 0, 4, Dw2Inval, Dw2Inval -bp, Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval -si, Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval -di, Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval -r8w, Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval -r9w, Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval -r10w, Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval -r11w, Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval -r12w, Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval -r13w, Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval -r14w, Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval -r15w, Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval +ax, Class=Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval +cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval +dx, Class=Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval +bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval +sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval +bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval +si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval +di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval +r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval +r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval +r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval +r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval +r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval +r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval +r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval +r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval // 32 bit regs -eax, Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval -ecx, Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval -edx, Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval -ebx, Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval -esp, Reg|Dword, 0, 4, 4, Dw2Inval -ebp, Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval -esi, Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval -edi, Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval -r8d, Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval -r9d, Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval -r10d, Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval -r11d, Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval -r12d, Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval -r13d, Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval -r14d, Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval -r15d, Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval -rax, Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0 -rcx, Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2 -rdx, Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1 -rbx, Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3 -rsp, Reg|Qword, 0, 4, Dw2Inval, 7 -rbp, Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6 -rsi, Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4 -rdi, Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5 -r8, Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8 -r9, Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9 -r10, Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10 -r11, Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11 -r12, Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12 -r13, Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13 -r14, Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14 -r15, Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15 +eax, Class=Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval +ecx, Class=Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval +edx, Class=Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval +ebx, Class=Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval +esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval +ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval +esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval +edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval +r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval +r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval +r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval +r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval +r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval +r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval +r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval +r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval +rax, Class=Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0 +rcx, Class=Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2 +rdx, Class=Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1 +rbx, Class=Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3 +rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7 +rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6 +rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4 +rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5 +r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8 +r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9 +r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10 +r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11 +r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12 +r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13 +r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14 +r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15 // Vector mask registers. k0, RegMask, 0, 0, 93, 118 k1, RegMask, 0, 1, 94, 119 @@ -283,23 +283,23 @@ bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval -// No Reg will make these registers rejected for all purposes except +// No Class=Reg will make these registers rejected for all purposes except // for addressing. This saves creating one extra type for RIP/EIP. rip, Qword, RegRex64, RegIP, Dw2Inval, 16 eip, Dword, RegRex64, RegIP, 8, Dw2Inval -// No Reg will make these registers rejected for all purposes except +// No Class=Reg will make these registers rejected for all purposes except // for addressing. riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval // fp regs. -st(0), Reg|Acc|Tbyte, 0, 0, 11, 33 -st(1), Reg|Tbyte, 0, 1, 12, 34 -st(2), Reg|Tbyte, 0, 2, 13, 35 -st(3), Reg|Tbyte, 0, 3, 14, 36 -st(4), Reg|Tbyte, 0, 4, 15, 37 -st(5), Reg|Tbyte, 0, 5, 16, 38 -st(6), Reg|Tbyte, 0, 6, 17, 39 -st(7), Reg|Tbyte, 0, 7, 18, 40 +st(0), Class=Reg|Acc|Tbyte, 0, 0, 11, 33 +st(1), Class=Reg|Tbyte, 0, 1, 12, 34 +st(2), Class=Reg|Tbyte, 0, 2, 13, 35 +st(3), Class=Reg|Tbyte, 0, 3, 14, 36 +st(4), Class=Reg|Tbyte, 0, 4, 15, 37 +st(5), Class=Reg|Tbyte, 0, 5, 16, 38 +st(6), Class=Reg|Tbyte, 0, 6, 17, 39 +st(7), Class=Reg|Tbyte, 0, 7, 18, 40 // Pseudo-register names only used in .cfi_* directives eflags, 0, 0, 0, 9, 49 rflags, 0, 0, 0, Dw2Inval, 49 |