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authorNick Clifton <nickc@redhat.com>2016-03-18 17:08:27 +0000
committerNick Clifton <nickc@redhat.com>2016-03-18 17:08:27 +0000
commit87bba7a5e0858048c9b8702c147094d1a7eba92f (patch)
tree08809f6cc67c4891352d12ae7302a6d2ce3e1933 /sim
parentFix the disassembly of the AArch64's OOR instruction as a MOV instruction. (diff)
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Fix thinko in new GET_VEC_ELEMENT macro.
* cpustate.c: (GET_VEC_ELEMENT): And fix thinko using macro arguments.
Diffstat (limited to 'sim')
-rw-r--r--sim/aarch64/ChangeLog1
-rw-r--r--sim/aarch64/cpustate.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog
index e8f8b4895b8..df1a3437691 100644
--- a/sim/aarch64/ChangeLog
+++ b/sim/aarch64/ChangeLog
@@ -7,6 +7,7 @@
(GET_VEC_ELEMENT): Fix off by one error checking for an invalid
element index.
(SET_VEC_ELEMENT): Likewise.
+ (GET_VEC_ELEMENT): And fix thinko using macro arguments.
* memory.c: Trace memory reads when --trace-memory is enabled.
Remove float and double load and store functions.
diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c
index 19f485e81ea..50a83c927d1 100644
--- a/sim/aarch64/cpustate.c
+++ b/sim/aarch64/cpustate.c
@@ -345,7 +345,7 @@ aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
#define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
do \
{ \
- if (element >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
+ if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
{ \
TRACE_REGISTER (cpu, \
"Internal SIM error: invalid element number: %d ",\