aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAlexandre Oliva <aoliva@redhat.com>2000-07-04 06:52:30 +0000
committerAlexandre Oliva <aoliva@redhat.com>2000-07-04 06:52:30 +0000
commite063aa3bd8d3712e37a287603d3256282c209def (patch)
tree7e016132f8291cc7f4fdb5f8d129816f2e58495e /sim/arm/armemu.h
parent* armemu.c (LoadSMult): Use WriteR15() to discard the least (diff)
downloadbinutils-gdb-e063aa3bd8d3712e37a287603d3256282c209def.tar.gz
binutils-gdb-e063aa3bd8d3712e37a287603d3256282c209def.tar.bz2
binutils-gdb-e063aa3bd8d3712e37a287603d3256282c209def.zip
* armemu.h (INSN_SIZE): New macro.
(SET_ABORT): Save CPSR in SPSR and set LR. * armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE. (WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode. * arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
Diffstat (limited to 'sim/arm/armemu.h')
-rw-r--r--sim/arm/armemu.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/sim/arm/armemu.h b/sim/arm/armemu.h
index ad89294ffac..de836cb4c78 100644
--- a/sim/arm/armemu.h
+++ b/sim/arm/armemu.h
@@ -73,6 +73,9 @@ extern ARMword isize;
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
+#define INSN_SIZE (TFLAG ? 2 : 4)
+#else
+#define INSN_SIZE 4
#endif
#define NFLAG state->NFlag
@@ -179,7 +182,13 @@ extern ARMword isize;
state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
ARMul_R15Altered (state) ; \
}
-#define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
+#define SETABORT(i,m,d) do { \
+ int SETABORT_mode = (m); \
+ ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
+ ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
+ | (i) | SETABORT_mode)); \
+ state->Reg[14] = temp - (d); \
+} while (0)
#ifndef MODE32
#define VECTORS 0x20