Modify the ARNM assembler to accept the omission of the immediate argument for the writeback form of the LDRAA and LDRAB mnemonics

This is a shorthand for the immediate argument being 0, as described here:
  https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication

This is because the instructions still have a use with an immediate
argument of 0, unlike loads without the PAC functionality. Currently,
the mnemonics are

  LDRAA Xt, [Xn, #<simm10>]!
  LDRAB Xt, [Xn, #<simm10>]!

After this patch they become

  LDRAA Xt, [Xn {, #<simm10>}]!
  LDRAB Xt, [Xn {, #<simm10>}]!

gas	* config/tc-aarch64.c (parse_address_main): Accept the omission of
	the immediate argument for ldraa and ldrab as a shorthand for the
	immediate being 0.
	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
	* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
	writeback form with no offset.
	* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
	error.

opcodes	* aarch64-opc.c (print_immediate_offset_address): Don't print the
	immediate for the writeback form of ldraa/ldrab if it is 0.
	* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
	* aarch64-opc-2.c: Regenerated.

4 files changed, 15 insertions, 3 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dc22f411154..d88aee324c2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-10-30  Delia Burduv   <delia.burduv@arm.com>
+
+	* aarch64-opc.c (print_immediate_offset_address): Don't print the
+	immediate for the writeback form of ldraa/ldrab if it is 0.
+	* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
+	* aarch64-opc-2.c: Regenerated.
+
 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-gen.c (operand_type_shorthands): Delete.
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 178d2108d7a..53d59461ad8 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -112,7 +112,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
-  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with an optional 10-bit scaled, signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 13-bit signed immediate (multiple of 16) offset"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 2e205e56a66..992a2af1b3a 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3063,7 +3063,12 @@ print_immediate_offset_address (char *buf, size_t size,
   if (opnd->addr.writeback)
     {
       if (opnd->addr.preind)
-	snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+        {
+	  if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
+            snprintf (buf, size, "[%s]!", base);
+          else
+	    snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+        }
       else
 	snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
     }
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ee36f1c9922..00168dd12e9 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5141,7 +5141,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
     Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index),	\
       "an address with 9-bit negative or unaligned immediate offset")	\
     Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\
-      "an address with 10-bit scaled, signed immediate offset")		\
+      "an address with an optional 10-bit scaled, signed immediate offset")		\
     Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\
       "an address with 11-bit signed immediate (multiple of 16) offset")\
     Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12),	\