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| author |   Repository mirror & CI <repomirrorci@gentoo.org> | 2018-07-17 21:47:54 +0000 |
|---|---|---|
| committer | Repository mirror & CI <repomirrorci@gentoo.org> | 2018-07-17 21:47:54 +0000 |
| commit | 1f7be5c011e3ddb7d7fa2d8822266b6112f0a621 (patch) | |
| tree | 45a1089b6fd97b678c04f9be21bf25b59f113a12 /metadata/md5-cache/sci-electronics/iverilog-0.9.7 | |
| parent | Merge updates from master (diff) | |
| download | gentoo-1f7be5c011e3ddb7d7fa2d8822266b6112f0a621.tar.gz gentoo-1f7be5c011e3ddb7d7fa2d8822266b6112f0a621.tar.bz2 gentoo-1f7be5c011e3ddb7d7fa2d8822266b6112f0a621.zip | |
2018-07-17 21:47:53 UTC
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-0.9.7')
| -rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-0.9.7 | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-0.9.7 b/metadata/md5-cache/sci-electronics/iverilog-0.9.7 new file mode 100644 index 000000000000..2f9b7366f42c --- /dev/null +++ b/metadata/md5-cache/sci-electronics/iverilog-0.9.7 @@ -0,0 +1,13 @@ +DEFINED_PHASES=install prepare +DEPEND=app-arch/bzip2 sys-libs/readline sys-libs/zlib +DESCRIPTION=A Verilog simulation and synthesis tool +EAPI=4 +HOMEPAGE=http://iverilog.icarus.com/ +IUSE=examples +KEYWORDS=~amd64 ~ppc ~sparc ~x86 +LICENSE=GPL-2 +RDEPEND=app-arch/bzip2 sys-libs/readline sys-libs/zlib +SLOT=0 +SRC_URI=ftp://icarus.com/pub/eda/verilog/v0.9/verilog-0.9.7.tar.gz +_eclasses_=desktop 1b286a7e7143d8c4ec89cd0d2743a097 epatch 9a5f039771f143195164a15a4faa41a1 estack 43ddf5aaffa7a8d0482df54d25a66a1f eutils b43d08fe0771faf2f5e7be19c2789d33 ltprune 607e058da37aa6dabfa408b7d61da72e multilib 97f470f374f2e94ccab04a2fb21d811e preserve-libs ef207dc62baddfddfd39a164d9797648 toolchain-funcs 1e35303c63cd707f6c3422b4493d5607 vcs-clean 2a0f74a496fa2b1552c4f3398258b7bf +_md5_=34bee9fd3fb9d2f5eceed4870d1f757c |