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* tcp/mips: Change TCG_AREG0 (fp -> s0)Stefan Weil2010-04-142-5/+6
| | | | | | | | | | | | | | | | Register fp (frame pointer) is a bad choice for compilations without optimisation, because the compiler makes heavy use of this register (so the resulting code crashes). Register s0 had been used for TCG_AREG1 in earlier releases, but was no longer used and is now free for TCG_AREG0. The resulting code works for compilations without optimisation (tested with qemu mips in qemu mips on x86 host). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/mips: fix branch offset during retranslationAurelien Jarno2010-03-291-19/+30
| | | | | | | | Branch offsets should only be overwritten during relocation, to support partial retranslation. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 6d8ff4d85ce2f3fc8a18dc8f077f73a4bd19a89a)
* tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno2010-03-191-4/+7
| | | | | | | | | | | | | | | | | | | | | Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes on ARM hosts. This is not a bug of this commit, but a latent bug revealed by this commit. The TCG code is called through a procedure call using the prologue and epilogue code. This code does not save and restore enough registers. The "Procedure Call Standard for the ARM Architecture" says: A subroutine must preserve the contents of the registers r4-r8, r10,  r11 and SP (and r9 in PCS variants that designate r9 as v6). The current code only saves and restores r9 to r11, and misses r4 to r8. The patch fixes that by saving r4 to r12. Theoretically there is no need to save and restore r12, but an even number of registers have to be saved as per EABI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 4e17eae9f2ee49833698aae2753c5bb041510870)
* tcg/mips: fix crash in tcg_out_qemu_ld()Aurelien Jarno2010-02-091-2/+2
| | | | | | | | | The address register is overriden when it corresponds to v0 and the fast path is taken, which leads to a crash. Fix that by using the a0 register instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit cca1af8c4d2ef6449fd61494ba2cb087b838011c)
* S/390 fake TCG implementationAlexander Graf2009-12-052-0/+174
| | | | | | | | | | | | Qemu won't let us run a KVM target without having host TCG support. Well, for now we don't have any so let's implement a fake target that only stubs out everything. I tried to keep the patch as close to Uli's source as possible, so whenever he feels like it he can easily diff his version against this one. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: initial mips supportAurelien Jarno2009-12-012-0/+1446
| | | | | | | | | | | | | | | | Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> A few words about design choices: * Two registers, at and t0, are reserved for TCG internal use. They are useful for bswap and 64-bit ops. * Most ops supports a constant argument with value 0, which is actually mapped to the zero register. * While the at register is available for constant loading, ops only support a limited range of constants. TCG does a better job doing the register allocation and constant loading by itself. There are plenty of registers available anyway. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: fix tcg_regset_{set,reset}_reg with more than 32 registersAurelien Jarno2009-11-241-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno2009-11-242-2/+2
| | | | | | This op only takes two arguments, not two. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: remove duplicate sar opcodeMagnus Damm2009-11-141-1/+0
| | | | | Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: improve output logAurelien Jarno2009-10-071-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: allocate s->op_dead_iargs dynamicallyAurelien Jarno2009-10-041-2/+1
| | | | | | | Similarly to what is already done in tcg_liveness_analysis() when USE_LIVENESS_ANALYSIS is not set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: remove dead codeAurelien Jarno2009-10-041-2/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: add support for ext{8,16}u_i32 TCG opsAurelien Jarno2009-10-042-0/+10
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno2009-10-042-0/+26
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: add ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno2009-10-042-3/+36
| | | | | | | | | | | | | | | | | | | | | Currently zero extensions ops are implemented by a and op with a constant. This is then catched in some backend, and replaced by a zero extension instruction. While this works well on RISC machines, this adds a useless register move on non-RISC machines. Example on x86: ext16u_i32 r1, r2 is translated into mov %eax,%ebx movzwl %bx, %ebx while the optimized version should be: movzwl %ax, %ebx This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be implemented in the backends to avoid emitting useless register moves. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert part of 6692b043198d58a12317009edb98654c6839f043Aurelien Jarno2009-09-301-8/+4
| | | | | | Committed by accident. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* TCG: fix DEF2 macroAurelien Jarno2009-09-301-5/+9
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: generates dec/inc instead of sub/add when possibleAurelien Jarno2009-09-271-9/+15
| | | | | | | We must take care that dec/inc do not compute CF, which is needed by add2/sub2. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/i386: optimize and $0xff(ff), regAurelien Jarno2009-09-271-0/+6
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/x86_64: generated dec/inc instead of sub/add when possibleAurelien Jarno2009-09-271-2/+14
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/ppc: always use tcg_out_callmalc2009-09-271-20/+10
| | | | Signed-off-by: malc <av1474@comtv.ru>
* ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues2009-09-261-0/+10
| | | | | | | This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Suppress some variants of English in commentsStefan Weil2009-09-252-4/+4
| | | | | | | Replace surpress, supress by suppress. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Compile TCG runtime library only onceBlue Swirl2009-09-203-77/+14
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: fix size of local variables in tcg_gen_bswap64_i64Stefan Weil2009-09-161-5/+4
| | | | | | | t0, t1 must be 64 bit values, not 32 bit. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* X86_64: Use proper jumps/calls when displacement exceeds +-2Gmalc2009-09-111-12/+19
| | | | Signed-off-by: malc <av1474@comtv.ru>
* When targeting PPU use rlwinm instead of andi. if possiblemalc2009-09-061-8/+54
| | | | | | andi. is microcoded and slow there. Signed-off-by: malc <av1474@comtv.ru>
* ARM back-end: Fix encode_immLaurent Desnogues2009-08-251-0/+2
| | | | | | | | | the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* ARM back-end: Handle all possible immediates for ALU opsLaurent Desnogues2009-08-221-5/+32
| | | | | | | | | | this patch handles all possible constants for immediate operand of ALU ops. I'm not very satisfied by the implementation. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* ARM back-end: Add TCG notLaurent Desnogues2009-08-222-0/+6
| | | | | | | | | | | this patch: - implements TCG not. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* rename DEBUG_TCG to CONFIG_DEBUG_TCGJuan Quintela2009-07-272-2/+2
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}Juan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Fix CONFIG_PROFILERBlue Swirl2009-07-211-5/+3
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix rbase initializationmalc2009-07-201-1/+1
| | | | Signed-off-by: malc <av1474@comtv.ru>
* this patch improves the ARM back-end in the following way:Laurent Desnogues2009-07-182-7/+37
| | | | | | | | | | - use movw/movt to load immediate values for ARMv7-A - implement add/sub/and/or/xor with immediate (only 8-bit) Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
* tcg: Fix tcg_gen_rotr_i64Aurelien Jarno2009-07-181-1/+1
| | | | | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* PPC 32/64 GUEST_BASE supportmalc2009-07-184-41/+127
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Fix LHZX opcode valuemalc2009-07-182-2/+2
| | | | Signed-off-by: malc <av1474@comtv.ru>
* Userspace guest address offsettingJuan Quintela2009-07-171-1/+1
| | | | | | Fix type in i386 tcg. Signed-off-by: Juan Quintela <quintela@redhat.com>
* Userspace guest address offsettingPaul Brook2009-07-177-33/+103
| | | | | | | | | | Re-implement GUEST_BASE support. Offset guest ddress space by default if the guest binary contains regions below the host mmap_min_addr. Implement support for i386, x86-64 and arm hosts. Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Paul Brook <paul@codesourcery.com>
* ARM host fixesPaul Brook2009-07-172-4/+4
| | | | | | Minor TCG cleanups and warning fixes for ARM hosts. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
| | | | | | | Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
* tcg: make sure NDEBUG is defined before including <assert.h>aurel322009-04-161-6/+7
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
* Add a --enable-debug-tcg option to configureaurel322009-04-132-4/+9
| | | | | | | | | | | | | This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUG from being defined) when passing an option to the configure script. This should help to prevent any accidental changes that enable DEBUG_TCGV in tcg/tcg.h from being committed in future, and may help to encourage testing with DEBUG_TCGV enabled. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7105 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-4/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
* Whack [LS]MWmalc2009-04-112-6/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove reserved registers from tcg_target_reg_alloc_ordermalc2009-04-111-3/+0
| | | | | | Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg/tcg.h: fix a few typosaurel322009-04-071-3/+3
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: add a CONST flag to TCG helpersaurel322009-04-062-4/+12
| | | | | | | | | | A const function only reads its arguments and does not use TCG globals variables. Hence a call to such a function does not save TCG globals variabes back to their canonical location. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7008 c046a42c-6fe2-441c-8c8c-71466251a162