diff options
Diffstat (limited to 'rpython/jit/backend/aarch64')
| -rw-r--r-- | rpython/jit/backend/aarch64/opassembler.py | 18 | ||||
| -rw-r--r-- | rpython/jit/backend/aarch64/regalloc.py | 2 |
2 files changed, 14 insertions, 6 deletions
diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py index e6383b2e06..27649cc914 100644 --- a/rpython/jit/backend/aarch64/opassembler.py +++ b/rpython/jit/backend/aarch64/opassembler.py @@ -382,8 +382,13 @@ class ResOpAssembler(BaseAssembler): value_loc, base_loc, index_loc, size_loc, ofs_loc = arglocs assert index_loc.is_core_reg() # add the base offset - if ofs_loc.value > 0: - self.mc.ADD_ri(r.ip0.value, index_loc.value, ofs_loc.value) + if ofs_loc.value != 0: + if check_imm_arg(ofs_loc.value): + self.mc.ADD_ri(r.ip0.value, index_loc.value, ofs_loc.value) + else: + # ofs_loc.value is too large for an ADD_ri + self.load(r.ip0, ofs_loc) + self.mc.ADD_rr(r.ip0.value, r.ip0.value, index_loc.value) index_loc = r.ip0 scale = get_scale(size_loc.value) self._write_to_mem(value_loc, base_loc, index_loc, scale) @@ -394,8 +399,13 @@ class ResOpAssembler(BaseAssembler): nsize = nsize_loc.value signed = (nsize < 0) # add the base offset - if ofs_loc.value > 0: - self.mc.ADD_ri(r.ip0.value, index_loc.value, ofs_loc.value) + if ofs_loc.value != 0: + if check_imm_arg(ofs_loc.value): + self.mc.ADD_ri(r.ip0.value, index_loc.value, ofs_loc.value) + else: + # ofs_loc.value is too large for an ADD_ri + self.load(r.ip0, ofs_loc) + self.mc.ADD_rr(r.ip0.value, r.ip0.value, index_loc.value) index_loc = r.ip0 # scale = get_scale(abs(nsize)) diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py index 7ecb455ec8..e87bd8a51e 100644 --- a/rpython/jit/backend/aarch64/regalloc.py +++ b/rpython/jit/backend/aarch64/regalloc.py @@ -557,7 +557,6 @@ class Regalloc(BaseRegalloc): assert boxes[3].getint() == 1 # scale ofs = boxes[4].getint() size = boxes[5].getint() - assert check_imm_arg(ofs) return [value_loc, base_loc, index_loc, imm(size), imm(ofs)] def _prepare_op_gc_load_indexed(self, op): @@ -567,7 +566,6 @@ class Regalloc(BaseRegalloc): assert boxes[2].getint() == 1 # scale ofs = boxes[3].getint() nsize = boxes[4].getint() - assert check_imm_arg(ofs) self.possibly_free_vars_for_op(op) self.free_temp_vars() res_loc = self.force_allocate_reg(op) |